Cortex-M3 Document

ARM에서 제공하는 Cortex-M3 Document

arm에서 제공하는 문서는 Generic User Guide와 Reference Manual 두가지 이며, 다행히(?) 다른 계열의 ARM 시리즈에 비해 Document가 비교적 가볍다. 따라서 시간이 된다면 한번 정도는 정독 해두어도 충분히 값어치가 있는 문서라고 할 수 있다.

 

1) Cortex-m3 Devices Generic User Guide : r2p1

  PDF version

 

1. Introduction
1.1. About the Cortex-M3 processor and core peripherals

1.1.1. System-level interface
1.1.2. Optional integrated configurable debug
1.1.3. Cortex-M3 processor features and benefits summary
1.1.4. Cortex-M3 core peripherals

2. The Cortex-M3 Processor
2.1. Programmers model

2.1.1. Processor mode and privilege levels for software execution
2.1.2. Stacks
2.1.3. Core registers
2.1.4. Exceptions and interrupts
2.1.5. Data types
2.1.6. The Cortex Microcontroller Software Interface Standard 

 

2.2. Memory model

2.2.1. Memory regions, types and attributes
2.2.2. Memory system ordering of memory accesses
2.2.3. Behavior of memory accesses
2.2.4. Software ordering of memory accesses
2.2.5. Optional bit-banding
2.2.6. Memory endianness
2.2.7. Synchronization primitives
2.2.8. Programming hints for the synchronization primitives

 

2.3. Exception model

2.3.1. Exception states
2.3.2. Exception types
2.3.3. Exception handlers
2.3.4. Vector table
2.3.5. Exception priorities
2.3.6. Interrupt priority grouping
2.3.7. Exception entry and return

 

 

2.4. Fault handling

2.4.1. Fault types
2.4.2. Fault escalation and hard faults
2.4.3. Fault status registers and fault address registers
2.4.4. Lockup

 

2.5. Power management

2.5.1. Entering sleep mode
2.5.2. Wakeup from sleep mode
2.5.3. The optional Wakeup Interrupt Controller
2.5.4. The external event input
2.5.5. Power management programming hints

 

3. The Cortex-M3 Instruction Set
3.1. Instruction set summary
3.2. CMSIS functions
3.3. About the instruction descriptions

3.3.1. Operands
3.3.2. Restrictions when using PC or SP
3.3.3. Flexible second operand
3.3.4. Shift Operations
3.3.5. Address alignment
3.3.6. PC‑relative expressions
3.3.7. Conditional execution
3.3.8. Instruction width selection

3.4. Memory access instructions

3.4.1. ADR
3.4.2. LDR and STR, immediate offset
3.4.3. LDR and STR, register offset
3.4.4. LDR and STR, unprivileged
3.4.5. LDR, PC‑relative
3.4.6. LDM and STM
3.4.7. PUSH and POP
3.4.8. LDREX and STREX
3.4.9. CLREX

 

3.5. General data processing instructions

3.5.1. ADD, ADC, SUB, SBC, and RSB
3.5.2. AND, ORR, EOR, BIC, and ORN
3.5.3. ASR, LSL, LSR, ROR, and RRX
3.5.4. CLZ
3.5.5. CMP and CMN
3.5.6. MOV and MVN
3.5.7. MOVT
3.5.8. REV, REV16, REVSH, and RBIT
3.5.9. TST and TEQ

 

3.6. Multiply and divide instructions

3.6.1. MUL, MLA, and MLS
3.6.2. UMULL, UMLAL, SMULL, and SMLAL
3.6.3. SDIV and UDIV

3.7. Saturating instructions

3.7.1. SSAT and USAT

 

3.8. Bitfield instructions

3.8.1. BFC and BFI
3.8.2. SBFX and UBFX
3.8.3. SXT and UXT

3.9. Branch and control instructions

3.9.1. B, BL, BX, and BLX
3.9.2. CBZ and CBNZ
3.9.3. IT
3.9.4. TBB and TBH

 

3.10. Miscellaneous instructions

3.10.1. BKPT
3.10.2. CPS
3.10.3. DMB
3.10.4. DSB
3.10.5. ISB
3.10.6. MRS
3.10.7. MSR
3.10.8. NOP
3.10.9. SEV
3.10.10. SVC
3.10.11. WFE
3.10.12. WFI

4. Cortex-M3 Peripherals
4.1. About the Cortex-M3 peripherals
4.2. Nested Vectored Interrupt Controller

4.2.1. Accessing the Cortex-M3 NVIC registers using CMSIS
4.2.2. Interrupt Set-enable Registers
4.2.3. Interrupt Clear-enable Registers
4.2.4. Interrupt Set-pending Registers
4.2.5. Interrupt Clear-pending Registers
4.2.6. Interrupt Active Bit Registers
4.2.7. Interrupt Priority Registers
4.2.8. Software Trigger Interrupt Register
4.2.9. Level-sensitive and pulse interrupts
4.2.10. NVIC usage hints and tips

 

4.3. System control block

4.3.1. Auxiliary Control Register
4.3.2. CPUID Base Register
4.3.3. Interrupt Control and State Register
4.3.4. Vector Table Offset Register
4.3.5. Application Interrupt and Reset Control Register
4.3.6. System Control Register
4.3.7. Configuration and Control Register
4.3.8. System Handler Priority Registers
4.3.9. System Handler Control and State Register
4.3.10. Configurable Fault Status Register
4.3.11. HardFault Status Register
4.3.12. MemManage Fault Address Register
4.3.13. BusFault Address Register
4.3.14. Auxiliary Fault Status Register
4.3.15. System control block usage hints and tips

 

4.4. System timer, SysTick

4.4.1. SysTick Control and Status Register
4.4.2. SysTick Reload Value Register
4.4.3. SysTick Current Value Register
4.4.4. SysTick Calibration Value Register
4.4.5. SysTick usage hints and tips

4.5. Optional Memory Protection Unit

4.5.1. MPU Type Register
4.5.2. MPU Control Register
4.5.3. MPU Region Number Register
4.5.4. MPU Region Base Address Register
4.5.5. MPU Region Attribute and Size Register
4.5.6. MPU access permission attributes
4.5.7. MPU mismatch
4.5.8. Updating an MPU region
4.5.9. MPU usage hints and tips

A. Cortex-M3 Options
A.1. Cortex-M3 implementation options

 

 

2) Cortex-M3 Technical Reference Manual :  r2p1

  PDF version

 

1. Introduction
1.1. About the processor
1.2. Features
1.3. Interfaces
1.4. Configurable options
1.5. Product documentation

 

1.5.1. Documentation
1.5.2. Design Flow
1.5.3. Architecture and protocol information

 

1.6. Product revisions

1.6.1. Differences in functionality between r0p0 and r1p0
1.6.2. Differences in functionality between r1p0 and r1p1
1.6.3. Differences in functionality between r1p1 and r2p0
1.6.4. Differences in functionality between r2p0 and r2p1 

 

2. Functional Description
2.1. About the functions
2.2. Interfaces

2.2.1. Bus interfaces
2.2.2. ETM interface
2.2.3. AHB Trace Macrocell interface
2.2.4. Debug Port AHB-AP interface 

 

3. Programmers Model
3.1. About the programmers model
3.2. Modes of operation and execution

3.2.1. Operating modes
3.2.2. Operating states
3.2.3. Privileged access and user access 

3.3. Instruction set summary

3.3.1. Cortex-M3 instructions
3.3.2. Load/store timings
3.3.3. Binary compatibility with other Cortex processors 

3.4. System address map

3.4.1. Private peripheral bus
3.4.2. Unaligned accesses that cross regions 

3.5. Write buffer
3.6. Exclusive monitor
3.7. Bit-banding

3.7.1. Directly accessing an alias region
3.7.2. Directly accessing a bit-band region 

3.8. Processor core register summary
3.9. Exceptions

3.9.1. Exception handling 

 

4. System Control
4.1. About system control
4.2. Register summary
4.3. Register descriptions

4.3.1. Auxiliary Control Register, ACTLR
4.3.2. CPUID Base Register, CPUID
4.3.3. Auxiliary Fault Status Register, AFSR 

 

5. Memory Protection Unit
5.1. About the MPU
5.2. MPU functional description
5.3. MPU programmers model

6. Nested Vectored Interrupt Controller
6.1. About the NVIC
6.2. NVIC functional description

6.2.1. Low power modes
6.2.2. Level versus pulse interrupts 

 

6.3. NVIC programmers model

6.3.1. Interrupt Controller Type Register, ICTR 

 

7. Debug
7.1. About debug

 

7.1.1. Cortex-M3 ROM table identification and entries
7.1.2. System Control Space
7.1.3. Debug register summary

 

7.2. About the AHB-AP

7.2.1. AHB-AP transaction types
7.2.2. AHB-AP programmers model 

 

7.3. About the Flash Patch and Breakpoint Unit (FPB)

7.3.1. FPB functional description
7.3.2. FPB programmers model 

 

8. Data Watchpoint and Trace Unit
8.1. About the DWT
8.2. DWT functional description
8.3. DWT Programmers Model

 

9. Instrumentation Trace Macrocell Unit
9.1. About the ITM
9.2. ITM functional description
9.3. ITM programmers model

9.3.1. ITM Trace Privilege Register, ITM_TPR 

 

10. Embedded Trace Macrocell
10.1. About the ETM

10.1.1. Features 

10.1.2. Configurable options

10.2. ETM functional description

10.2.1. Resources
10.2.2. Timestamp format
10.2.3. Periodic synchronization
10.2.4. Data and instruction address compare resources
10.2.5. External inputs
10.2.6. Start/stop block
10.2.7. Triggering
10.2.8. Interfaces
10.2.9. Operation 

10.3. ETM Programmers model

10.3.1. Modes of operation and execution
10.3.2. Register summary
10.3.3. Main Control Register, ETMCR
10.3.4. Configuration Code Register, ETMCCR
10.3.5. System Configuration Register, ETMSCR
10.3.6. TraceEnable Control 1 Register, ETMTECR1
10.3.7. ID Register, ETMIDR
10.3.8. Configuration Code Extension Register, ETMCCER
10.3.9. TraceEnable Start/Stop EmbeddedICE Control Register, ETMTESSEICR
10.3.10. Device Power-Down Status Register, ETMPDSR
10.3.11. Integration Test Miscellaneous Inputs, ITMISCIN
10.3.12. Integration Test Trigger Out, ITTRIGOUT
10.3.13. ETM Integration Test ATB Control 2, ETM_ITATBCTR2
10.3.14. ETM Integration Test ATB Control 0, ETM_ITATBCTR0 

 

11. Trace Port Interface Unit
11.1. About the Cortex-M3 TPIU
11.2. TPIU functional description

11.2.1. TPIU block diagrams
11.2.2. TPIU Formatter
11.2.3. Serial Wire Output format 

11.3. TPIU programmers model

11.3.1. Asynchronous Clock Prescaler Register, TPIU_ACPR
11.3.2. Formatter and Flush Status Register, TPIU_FFSR
11.3.3. Formatter and Flush Control Register, TPIU_FFCR
11.3.4. TRIGGER
11.3.5. Integration ETM Data
11.3.6. ITATBCTR2
11.3.7. Integration ITM Data
11.3.8. ITATBCTR0
11.3.9. Integration Mode Control, TPIU_ITCTRL
11.3.10. TPIU_DEVID
11.3.11. TPIU_DEVTYPE